The author describes computing strategic tasks that are used for ensuring defense and national security, the most important scientific, technical, biomedical and sociology tasks. Most typically, these are capability-based tasks. Supercomputers for their solution are respectively called Technical Capability, i.e. machines of extreme technical capabilities. Machines of this segment are also called High End Computers (HEC), and in our terminology - strategic supercomputers (SCs). Moving to the engineering level, author says that for tasks with good spatio-temporal work with memory, cache memory and schemes for automatically pre-loading data into the cache memory can be effectively used. This can significantly reduce the average memory access time of several hundred processor cycles to fractions of a processor cycle. Such tasks are usually called computational or cache-friendly (cach-friendly) - CF tasks. On tasks with poor spatio-temporal work with memory, the cache memory is useless, so each memory access is hundreds of processor cycles, the processor is idle because of this, and therefore the real performance is in units or even a fraction of a percent of the peak. Such tasks are historically called tasks with intensive irregular work with memory – Data intensive tasks (DIS-tasks). The given examples of spatially-temporal work with task memory and real characteristics of equipment operation in such different modes are given in order to illustrate that in practice different types of supercomputers are needed, for example, for CF- and DIS-tasks.
| Published in |
Journal of Electrical and Electronic Engineering (Volume 7, Issue 3)
This article belongs to the Special Issue Science Innovation |
| DOI | 10.11648/j.jeee.20190703.12 |
| Page(s) | 82-86 |
| Creative Commons |
This is an Open Access article, distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution and reproduction in any medium or format, provided the original work is properly cited. |
| Copyright |
Copyright © The Author(s), 2019. Published by Science Publishing Group |
Virtualization, Information Security, Supercomputers, Security Descriptor
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APA Style
Andrey Molyakov. (2019). New-age Supercomputers: Hi-Speed Networks and Information Security. Journal of Electrical and Electronic Engineering, 7(3), 82-86. https://doi.org/10.11648/j.jeee.20190703.12
ACS Style
Andrey Molyakov. New-age Supercomputers: Hi-Speed Networks and Information Security. J. Electr. Electron. Eng. 2019, 7(3), 82-86. doi: 10.11648/j.jeee.20190703.12
AMA Style
Andrey Molyakov. New-age Supercomputers: Hi-Speed Networks and Information Security. J Electr Electron Eng. 2019;7(3):82-86. doi: 10.11648/j.jeee.20190703.12
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Download@article{10.11648/j.jeee.20190703.12,
author = {Andrey Molyakov},
title = {New-age Supercomputers: Hi-Speed Networks and Information Security},
journal = {Journal of Electrical and Electronic Engineering},
volume = {7},
number = {3},
pages = {82-86},
doi = {10.11648/j.jeee.20190703.12},
url = {https://doi.org/10.11648/j.jeee.20190703.12},
eprint = {https://article.sciencepublishinggroup.com/pdf/10.11648.j.jeee.20190703.12},
abstract = {The author describes computing strategic tasks that are used for ensuring defense and national security, the most important scientific, technical, biomedical and sociology tasks. Most typically, these are capability-based tasks. Supercomputers for their solution are respectively called Technical Capability, i.e. machines of extreme technical capabilities. Machines of this segment are also called High End Computers (HEC), and in our terminology - strategic supercomputers (SCs). Moving to the engineering level, author says that for tasks with good spatio-temporal work with memory, cache memory and schemes for automatically pre-loading data into the cache memory can be effectively used. This can significantly reduce the average memory access time of several hundred processor cycles to fractions of a processor cycle. Such tasks are usually called computational or cache-friendly (cach-friendly) - CF tasks. On tasks with poor spatio-temporal work with memory, the cache memory is useless, so each memory access is hundreds of processor cycles, the processor is idle because of this, and therefore the real performance is in units or even a fraction of a percent of the peak. Such tasks are historically called tasks with intensive irregular work with memory – Data intensive tasks (DIS-tasks). The given examples of spatially-temporal work with task memory and real characteristics of equipment operation in such different modes are given in order to illustrate that in practice different types of supercomputers are needed, for example, for CF- and DIS-tasks.},
year = {2019}
}
TY - JOUR T1 - New-age Supercomputers: Hi-Speed Networks and Information Security AU - Andrey Molyakov Y1 - 2019/10/09 PY - 2019 N1 - https://doi.org/10.11648/j.jeee.20190703.12 DO - 10.11648/j.jeee.20190703.12 T2 - Journal of Electrical and Electronic Engineering JF - Journal of Electrical and Electronic Engineering JO - Journal of Electrical and Electronic Engineering SP - 82 EP - 86 PB - Science Publishing Group SN - 2329-1605 UR - https://doi.org/10.11648/j.jeee.20190703.12 AB - The author describes computing strategic tasks that are used for ensuring defense and national security, the most important scientific, technical, biomedical and sociology tasks. Most typically, these are capability-based tasks. Supercomputers for their solution are respectively called Technical Capability, i.e. machines of extreme technical capabilities. Machines of this segment are also called High End Computers (HEC), and in our terminology - strategic supercomputers (SCs). Moving to the engineering level, author says that for tasks with good spatio-temporal work with memory, cache memory and schemes for automatically pre-loading data into the cache memory can be effectively used. This can significantly reduce the average memory access time of several hundred processor cycles to fractions of a processor cycle. Such tasks are usually called computational or cache-friendly (cach-friendly) - CF tasks. On tasks with poor spatio-temporal work with memory, the cache memory is useless, so each memory access is hundreds of processor cycles, the processor is idle because of this, and therefore the real performance is in units or even a fraction of a percent of the peak. Such tasks are historically called tasks with intensive irregular work with memory – Data intensive tasks (DIS-tasks). The given examples of spatially-temporal work with task memory and real characteristics of equipment operation in such different modes are given in order to illustrate that in practice different types of supercomputers are needed, for example, for CF- and DIS-tasks. VL - 7 IS - 3 ER -
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